1. Field
The present invention generally relates to an electrical circuit, and more particularly to a reconfigurable circuit which can be dynamically reconfigured.
2. Description of Related Art
In a dynamic reconfigurable circuit using processing elements, multiple processing elements are arranged in an array manner and connected to each other by a data network disposed vertically and horizontally. The arithmetic function of the processing elements and the connection relationship between the processing elements made via the network are set so as to be reconfigurable by software. Around the processor element array section, there are provided a configuration memory that stores configuration data on the processor element array section, a controller that controls switching of dynamic reconfiguration, and the like.
In the dynamic reconfigurable circuit having the above configuration, the basic component of the reconfigurable structure is a processor element. Thus, as compared to a FPGA (Field Programmable Gate Array) using a single gate or the like as its basic component, the dynamic reconfigurable circuit has considerably great granularity (modifiable unit size). Further, since the processing elements are arranged in an array manner, arithmetic operations can be executed in parallel, thus allowing high-speed execution of a heavy arithmetic processing, such as complex computation and product sum computation.
There are two different methods for supplying an immediate value (a fixed value specified in the program) to a processor element of the dynamic reconfigurable circuit. According to the first method, an immediate value is preliminarily stored in a data register connected to the data network and then supplied from the data register through the data network to a data input port of the processor element. According to the second method, an immediate value is defined and set as part of configuration data stored in the configuration memory, and then supplied from the configuration memory to an configuration data input port of the processor element.
According to the first method, the data network is used to supply an immediate value to the processor element. The number of connections between the processing elements that can be connected to each other via the data network is limited according to the data network configuration. When part of the data network is used to supply an immediate value, the upper limit number of connections between the processing elements decreases. That is, the modifiable-connection performance is lowered due to the data network resource consumption, and data transfer between the processing elements is affected. As such, necessary data may not be transferred.
According to the second method, immediate values in configuration data are defined and set for each processor element. Accordingly, when multiple processing elements use the same immediate value, the immediate values corresponding to the multiple processing elements must be defined and set in the configuration data in a repeated manner. Further, the immediate value set in configuration data is fixed. While the dynamic reconfigurable circuit operates according to the configuration data, the immediate value cannot be varied.